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TDA9103
DEFLECTION PROCESSOR FOR MULTISYNC MONITOR
. . . . . . . . . . . . . . . . . . . . . .
HORIZONTAL
DUAL PLL CONCEPT 150kHz MAXIMUM FREQUENCY SELF-ADAPTIVE (EX : 30 TO 85kHz) X-RAY PROTECTION INPUT DC ADJUSTABLE DUTY-CYCLE INTERNAL 1st PLL LOCK/UNLOCK IDENTIFICATION 4 OUTPUTS FOR S-CORRECTION WIDE RANGE DC CONTROLLED H-POSITION
T his IC, combined with TDA9205 (RG B preamp), STV9420/21 or 22 (O.S.D. processor), ST7271 (micro controller) and TDA8172 (vertical booster), allows to realize very simple and high quality multimodes or multisync monitors.
ON/OFF SWITCH (FOR PWR MANAGEMENT)
TWO H-DRIVE POLARITIES
VERTICAL
VERTICAL RAMP GENERATOR 50 TO 150Hz AGC LOOP DC CONTROLLED V-AMP, V-POS, S-AMP AND SCENTERING ON/OFF SWITCH SHRINK42 (Plastic Package) ORDER CODE : TDA9103
B+ REGULATOR
INTERNAL PWM GENERATOR FOR B+ CURRENT MODE STEP-UP CONVERTER DC ADJUSTABLE B+ VOLTAGE OUTPUT PULSES SYNCHRONISED ON HORIZONTAL FREQUENCY
PIN CONNECTIONS
PLL2C H-DUTY HFLY HGND HREF S4 S3 S2 S1 C0 R0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
ISENSE COMP REGIN B+-ADJ KEYST E/W-AMP E/WOUT PLL1INHIB VSYNC V-POS VDCOUT V-AMP VOUT VS-CENT VS-AMP VCAP VREF VAGCCAP VGND SBLKOUT B+OUT
9103-01.AI
INTERNAL MAXIMUM CURRENT LIMITATION
VERTICAL PARABOLA GENERATOR WITH DC CONTROLLED KEYSTONE AND AMPLITUDE
EWPCC
GENERAL
ACCEPT POS. OR NEG. H AND V SYNC POLARITIES SEPARATED H AND V TTL INPUT SAFETY BLANKING OUTPUT
DESCRIPTION
The TDA9103 is a monolithic integrated circuit assembled in a 42 pins shrunk dual in line plastic package. This IC controls all the functions related to the horizontal and vertical deflection in multimodes or multisync monitors. As can be seen in the block diagram, the TDA9103 includes the following functions : - Positive or Negative sync polarities, - Auto-sync horizontal processing, - H-PLL lock/unlock identification, - Auto-sync Vertical processing, - East/West signal processing block, - B+ controller, - Safety blanking output. May 1996
PLL1F HLOCK-CAP FH-MIN H-POS XRAY-IN HSYNC VCC GND H-OUTEM H-OUTCOL
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TDA9103
PIN-OUT DESCRIPTION
Pin N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Name PLL2C H-DUTY H-FLY H-GND H-REF S4 S3 S2 S1 C0 R0 PLL1F HLOCK-CAP FH-MIN H-POS XRAY-IN H-SYNC VCC GND H-OUTEM H-OUTCOL B+ OUT SBLK OUT VGND VAGCCAP VREF VCAP VS-AMP VS-CENT VOUT V-AMP VDCOUT V-POS VSYNC PLL1INHIB E/WOUT E/W-AMP KEYST B+ ADJ REGIN COMP ISENSE Function Second PLL Loop Filter DC Control of Horizontal Drive Output Pulse Duty-cycle. If this pin is grounded, the horizontal and vertical outputs are inhibited. By connecting a capacitor on this pin a soft-start function may be realized on h-drive output. Horizontal Flyback Input (positive Polarity) Horizontal Section Ground. Must be connected only to components related to H blocks. Horizontal Section Reference Voltage. Must be filtered by capacitor to Pin 4 Hor S-CAP Switching Hor S-CAP Switching Hor S-CAP Switching Hor S-CAP Switching Horizontal Oscillator Capacitor. To be connected to Pin 4. Horizontal Oscillator Resistor. To be connected to Pin 4. First PLL Loop Filter. To be connected to Pin 4. First PLL Lock/Unlock Time Constant Capacitor. Capacitor filtering the frequency change detected on Pin13. When frequency is changing, a blanking pulse is generated on Pin 23, the duration of this pulse is proportionnal to the capacitor on Pin 13. To be connected to Pin 4. DC Control for Free Running Frequency Setting. Comming from DAC output or DC voltage generated by a resistor bridge connected between Pin 5 and 4. DC Control for Horizontal Centering X-RAY Protection Input (with internal latch function) TTL Horizontal Sync Input Supply Voltage (12V Typical) Ground Horizontal Drive Output (emiter of internal transistor). See description on pages 15-16. Horizontal Drive Output (open collector of internal transistor). See description on pages 15-16. B+ PWM Regulator Output Safety Blanking Output. Activated during frequency changes, when X-RAY input is triggered or when VS is too low. Vertical Section Signal Ground Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator Vertical Section Reference Voltage Vertical Sawtooth Generator Capacitor DC Control of Vertical S Shape Amplitude DC Control of Vertical S Centering Vertical Ramp Output (with frequency independant amplitude and S-correction) DC Control of Vertical Amplitude Adjustment Vertical Position Reference Voltage Output Temperature Matched with V-AMP Output DC Control of Vertical Position Adjustment Vertical TTL Sync Input TTL Input for PLL1 Output Current Inhibition (To be used in case of comp sync input signal) East/West Pincushion Correction Parabola Output DC Control of East/West Pincushion Correction Amplitude DC Control of Keystone Correction DC Control of B+ Adjustment Regulation Input of B+ Control Loop B+ Error Amplifier Output for Frequency Compensation and Gain Setting Sensing of External B+ Switching Transistor Emiter Current
2/27
9103-01.TBL
TDA9103
BLOCK DIAGRAM
HLOCK-CAP H-OUTCOL PLL1INHIB H-OUTEM H-DUTY FH-MIN
PLL2C
H-POS
PLL1F
HFLY
R0
C0
S4
S3
S2
8
35
15
12
11
10
14
13
3
1
2
20
21
6
7
HS YNC 17
INPUT INTERFACE
1s t P HASE COMP
VCO
2nd P HASE COMP
P ULSE S HAPER
OUTP UT BUFFER
H FREQUENCY
S1
9 23 S BLKOUT 39 B+-ADJ 42 IS ENSE
LOCK DETECT XRAY-IN 16 HREF HGND
5
VREF H-VREF R
4
BANDGAP VREF 26 VGND 24 V-VREF
SAFETY P ROCES S OR VCC Outputs Inhibition
EA
22 B+OUT
S
41 COMP 40 REGIN
P ARABOLA GENERATOR VSYNC 34 INPUT INTERFACE
19 18
36 E/WOUT
VERTICAL OS CILLATOR
27 25
S CORRECTION
29 28 33 31 30 32 38 37
TDA9103
9103-02.EPS
V-AMP
VDCOUT
VOUT
GND
VCC
VCAP
VS-AMP
KEYST
VAGCCAP
VS-CENT
E/W-AMP
V-POS
3/27
TDA9103
QUICK REFERENCE DATA
Parameter Horizontal Frequency Range Autosynch Frequency Range (for Given R0, C0) Hor Sync Polarity Input Compatibility with Composite Sync on H-SYNC Input Lock/Unlock Identification on 1st PLL DC Control for H-Position X-RAY Protection Hor DUTY Adjust Stand-by Function Hor S-CAP Switching Control Two Polarities H-Drive Outputs Supply Voltage Monitoring PLL1 Inhibition Possibility Safety Blanking Output Vertical Frequency Range Vertical Autosync Range (for a Given Capacitor Value) Vertical -S- Correction Vertical -C- Correction Vertical Amplitude Adjustment Vertical Position Adjustment Automatic B+ Adjustment Control Loop B+ Adjustment East/West Parabola Output PCC (Pin Cushion Correction) Amplitude Adjustment Keystone Adjustment Reference Voltage Mode Detection Dynamic Focus Blanking Output
Notes : 1. See application diagram. 2. One for Horizontal section and one for Vertical section.
Value 15 to 150 1 to 3.7 YES YES (1) YES YES YES YES YES YES YES YES YES YES 35 to 200 50 to 150 YES YES YES YES YES YES YES YES YES YES (2) NO NO NO
Unit kHz FH
Hz Hz
4/27
9103-02.TBL
TDA9103
ABSOLUTE MAX RATING
Symbol VCC VIN Supply Voltage (Pin 18) Max Voltage on Pins 2, 14, 15, 28, 29, 31, 33, 37, 38, 39 Pin 3 Pins 17, 34 Pin 40 Pin 42 Pin 16 Parameter Value 13.5 8 1.8 6 8 8 5.5 2 300 -40, +150 150 0, +70 Unit V V
VESD
ESD Succeptibility Human Body Model, 100pF Discharge through 1.5k EIAJ Norm, 200pF Discharge through 0 Storage Temperature Max Operating Junction Temperature Operating Temperature
kV V C C C
9103-03.TBL 9103-05.TBL 9103-04.TBL
Tstg Tj Toper
THERMAL DATA
Symbol Rth (j-a) Parameter Junction-Ambient Thermal Resistance Max. Value 65 Unit C/W
HORIZONTAL SECTION Operating conditions
Symbol VCO R0min C0min Fmax HsVR Oscillator Resistor Min Value Oscillator Capacitor Min Value Maximum Oscillator Frequency Horizontal Sync Input Voltage Range Pin 17 0 Pin 11 Pin 10 6 390 150 5.5 k pF kHz V S 25 % Parameter Test conditions Min. Typ. Max. Unit
INPUT SECTION MinD Mduty Minimum Input Pulses Duration Maximum Input Signal Duty Cycle Pin 17 Pin 17 0.7
OUTPUT SECTION I3m IS1 to IS4 VS1 to VS4 HOI1 HOI2 Maximum Input Peak Current on Pin 3 Maximum Current on S1 to S4 Outputs Maximum Voltage on S1 to S4 Outputs Horizontal Drive Output Max Current Horizontal Drive Output Max Current Pins 6 to 9 Pins 6 to 9 Pin 20, sourced current Pin 21, sunk current 2 0.5 VCC 20 20 mA mA V mA mA
DC CONTROL VOLTAGES DCadj DC Voltage Range on DC Controls VREF-H = 8V, Pins 2-14-15 2 6 V
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TDA9103
Electrical Characteristics (VCC = 12V, Tamb = 25C)
Symbol Parameter Test conditions Min. Typ. Max. Unit SUPPLY AND REFERENCE VOLTAGES VCC ICC VREF-H IREF-H VREF-V IREF-V Supply Voltage Supply Current Reference Voltage for Horizontal Section Max Sourced Current on VREF-H Reference Voltage for Vertical Section Max Sourced Current on VREF-V Pin 18 Pin 18, See Figure 1 Pin 5, I = 2mA Pin 5 Pin 26, I = 2mA Pin 26 7.4 8 7.4 10.8 12 40 8 13.2 60 8.6 5 8.6 5 V mA V mA V mA
INPUT SECTION/PLL1 VINTH VVCO VCOG Hph FFadj S1th S2th S3th S4th F0 Hor Input Threshold Voltage Pin 17 VCO Control Voltage Range VCO Gain, dF/dV Pin 12 Horizontal Phase Adj Range (Pin 15) Free Running Frequency Adj Range (Pin 14) VCO Input Voltage for S1 Switching VCO Input Voltage for S2 Switching VCO Input Voltage for S3 Switching VCO Input Voltage for S4 Switching Free Running Frequency Low level voltage High level voltage VREF-H = 8V, Pin 12 R0 = 6.49k, C0 = 680pF % of Hor period Without H-sync Signal Pin 12 voltage, V REF-H = 8V Pin 12 voltage, V REF-H = 8V Pin 12 voltage, V REF-H = 8V Pin 12 voltage, V REF-H = 8V V14 = VREF/2 R0 = 6.49k C0 = 680pF Pins 6 to 9, I = 0.5mA See conditions on Figure 1 28 94 V V35 V35 0.8 2 1.85 2.25 2.9 3.5 23.5 0.8 2 1.6 15 12.5 20 2 2.4 3 3.7 25 2.25 2.65 3.3 3.9 27.5 6.2 V V V kHz/V % % V V V V kHz
VS1D to VS4D CR
Low Level Output Voltage on S1 to S4 Outputs PLL1 Capture Range (F0 = 27kHz) Fh Min Fh Max PLL 1 Inhibition (Pin 35) PLL ON PLL OFF
0.2
0.4
V kHz
PLLinh
SECOND PLL AND HORIZONTAL OUTPUT SECTION FBth Hjit HDmin HDmin HDvd HDem XRAYth ISblkO VSblkO Vphi2 VOFF Flyback Input Threshold Voltage Horizontal Jitter Minimum Hor Drive Output Duty-cycle Maximum Hor Drive Output Duty-cycle Horizontal Drive Low Level Output Voltage Horizontal Drive High Level Output Voltage (output on Pin 20) X-RAY Protection Input Threshold Voltage Maximum Output Current on Safety Blanking Output Low-Level Voltage on Safety Blanking Output Internal Clamping Voltage on 2nd PLL Loop Filter Output (Pin 1) Pin 2 Threshold Voltage to Stop H-out, V-out B+out and to Activate S-BLK.OFF Mode when V2 < VOFF Pin 20 or 21, V2 = 2V Pin 20 or 21, V2 = 6V V21-V20, Iout = 20mA, Pin 20 to GND Pin 21 to VCC, IOUT = 20mA Pin 16 I23 V23 with I23 = 10mA Vmin Vmax V2 0.25 1.6 3.2 1 9.5 45 Pin 3 0.65 0.75 100 30 50 1.1 10 1.6 1.8 10 0.5 35 1.7 V ppm % % V V V mA V V V V
9103-06.TBL
6/27
TDA9103
B+ SECTION Operating Conditions
Symbol EAOI FeedRes Parameter Maximum Error Amplifier Output Current Minimum Feedback Resistor Test conditions Sourced by Pin 41 Sunk by Pin 41 Resistor between Pins 40 and 41 5 Min. Typ. Max. 0.5 2 Unit
9103-07.TBL 9103-09.TBL 9103-08.TBL
mA mA k
Electrical Characteristics (VCC = 12V, Tamb = 25C)
Symbol OLG UGBW IRI EAOI CSG MCEth ISI Tonmax B+OSV IVREF VREFADJ Parameter Error Amplifier Open Loop Gain Unity Gain Bandwidth Regulation Input Bias Current Maximum Guaranted Error Amplifier Output Current Current Sense Input Voltage Gain Max Curent Sense Input Threshold Voltage Current Sense Input Bias Current Maximum External Power Transistor on Time B+ Output Low Level Saturation Voltage Internal Reference Voltage Internal Reference Voltage Adjustment Range Test conditions At low frequency (see Note 1) (see Note 1) Current sourced by Pin 40 (PNP base) Current sourced by Pin 41 Current sunk by Pin 41 Pin 42 Pin 42 Current sunk by Pin 42 (NPN base) % of H-period @ f0 = 27kHz V22 with I22 = 10mA On error amp (+) input for V39 = 4V 2V < V39 < 6V 0.5 2 3 1.2 1 75 0.25 4.9 14 V A % V V % Min. Typ. 85 6 0.2 Max. Unit dB MHz A mA mA
EAST WEST PARABOLA GENERATOR Electrical Characteristics (VCC = 12V, Tamb = 25C)
Symbol Vsym Parameter Parabola Symetry Adjustment Capability (for Keystone Adjustment ; with Pin 38) Test conditions See Figure 2 ; internal voltage V38 = 2V V38 = 4V V38 = 6V See Figure 2 ; V37 = 4V V38 = 2V V38 = 6V V38 = 4.3V, V28 = 2V V37 = 2V 2V < V37 < 6V 3.3 2.4 Min. Typ. Max. Unit V 3.2 3.5 3.8 2.3 2.0 V 3.8 3 4.3
Kadj
Keystone Adjustment Capability B/A ratio A/B ratio Parabola Amplitude Adjustment Capability Maximum Amplitude on Pin 36 Maximum Ratio between Max and Min
Paramp
7/27
TDA9103
VERTICAL SECTION Operating Conditions
Symbol VSVR Parameter Vertical Sync Input Voltage Range Test conditions On Pin 34 Min. 0 Typ. Max. 5.5 Unit V
9103-10.TBL 9103-11.TBL
Electrical Characteristics (VCC = 12V, Tamb = 25C)
Symbol IBIASP IBIASN VSth VSBI VRB VRT VRTF IR27 Parameter Pin 23-28-29 Bias Current (Current Sourced by PNP Base) Pin 31 Bias Current (Current Sunk by NPN Base) Vertical Sync Input Threshold Voltage Vertical Sync Input Bias Current (Current Sourced by PNP Base) Voltage at Ramp Bottom Point Voltage at Ramp Top Point (with Sync) Voltage at Ramp Top Point (without Sync) Output Current Range on Pin 27 during Ramp Charging Time. Current to Charge Capacitor between Pin 27 and Ground Minimum Vertical Sync Pulse Width Vertical Sync Input Maximum Duty-cycle Vertical Sawtooth Discharge Time Duration Vertical Free Running Frequency (V28 = 2V) AUTO-SYNC Frequency Range (see Note 3) Ramp Amplitude Thermal Drift Ramp Amplitude Drift Versus Frequency Ramp Linearity on Pin 27 I27/I 27 Minimum Load on Pin 25 for less than 1% Vertical Amplitude Drift Vertical Position Adjustment Range Voltage on Pin 32 Max Current on Vertical Position Control Output (Pin 32) Vertical Output Voltage Range (on Pin 30) (Peak to Peak Voltage on Pin 30) DC Voltage on Vertical Output (Pin30) Vertical Output Maximum Output Current Max Vertical S-Correction Amplitude (V28 = 2V Inhibits S-CORR; V28 = 6V gives Maximum S-CORR) (see Figure 3) C-Correction Adjustment Range Voltage on Pin 27 for Maximum Slope on the Ramp (with S-Correction) (see Figure 4) Test conditions For V23-28-29 = 2V For V31 = 6V Pin 34; High-level Low-level V34 = 0.8V On Pin 27 On Pin 27 On Pin 27 V28 = 2V (Note 2), 2V < V27 < 5V Min current Max current Pin 34 Pin 34 On Pin 27, with 150nF cap Measured on Pin 27 Cosc (Pin27) = 150nF With C27 = 150nF 5% On Pin 30 (see Note 1) (0C < Tamb < 70C) V31 = 6V, C27 = 150nF 50Hz < F < 120Hz V28 = 2V, V25 = 4.3V 2.5V < V27 < 4.5V 50 V33 = 2V V33 = 4V V33 = 6V 3.2 3.5 3.8 2 2 3 4 7/16 5 -4 +4 3 3.5 4 3.3 2 0.8 1 2/8 5/8 VRT-0.1 Min. Typ. 2 0.5 Max. Unit A A V V A VREF-V VREF-V V A A S % S Hz Hz ppm/C ppm/Hz % M V V V mA V V V VREF-V mA % % V V V
VSW VSmDut VSTD VFRF ASFR RATD RAFD Rlin Rload Vpos IVPOS Vor VOUTDC V0I dVS Ccorr
100 5
15 135
20
15 85 100 50 100 200 0.5 150
3.65
V31 = 2V V31 = 4V V31 = 6V See Note 4 On Pin 30 V/V30pp at T/4 V/V30pp at 3T/4 V29 = 2V V29 = 4V V29 = 6V
2.2
3.75
Notes : 1. These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes characterization on batches comming from corners of our processes and also temperature characterization. 2. When 2V are applied on Pin 28 (Vertical S-Correction control), then the S-Correction is inhibited, consequently the sawtooth have a linear shape. 3. It is the frequency range for which the VERTICAL OSCILLATOR will automatically synchronize, using a single capacitor value on Pin 27 and with a constant ramp amplitude. 4. Typically 3.5V for Vertical reference voltage typical value (8V).
8/27
S6 12V 12V 15 k 15 k 15 k 4.7k 15 k
1.8k
6.49k
10nF 220nF 22nF
3 20 6 9 21 1 2 7 8 13
Figure 1 : Testing Circuit
4.7 F
15 10 12 11 14
680pF 1%
35
17
INPUT INTERFACE VCO
1st PHASE COMP
2nd PHASE COMP
PULSE SHAPER
OUTPUT BUFFER
H FREQUENCY 4.7k
23
12V
LOCK DETECT
39 VREF R
22
16
5
42 3.9k 12V S 470pF 10k 41
40
2.2 F EA SAFETY PROCESSOR VCC Outputs Inhibition
H-VREF
4
BANDGAP
26
2.2 F
V-VREF
24
47k 10k PARABOLA GENERATOR
36
34
INPUT INTERFACE 25
29 28 33 31 30
VERTICAL OSCILLATOR
S CORRECTION
TDA9103
32 38 37
19
18
27
12V S5
150nF 1%
470nF 1%
TDA9103
9/27
9103-54.EPS
TDA9103
Figure 2 : Keystone Adjustment
V36 A V38 = 2V V38 = 4V V38 = 6V B
V27 3.8 3.5 3.2
Figure 3 : S Amplitude Adjustment
V30 V
V30pp
Figure 4 : C Correction Adjustment
V27
4.0V 3.5V 3.0V
9103-05.AI
0
T
10/27
9103-04.AI
0
T/4
T/2
3T/4
T
V increase when V28 increase. V = 0 when V28 = 0.
9103-03.AI
TDA9103 OPERATING DESCRIPTION
GENERAL CONSIDERATIONS Power Supply The typical value of the power supply voltage VCC is 12V. Perfect operation is obtained if VCC is maintained in the limits : 10.8V 13.2V. In order to avoid erratic operation of the circuit during the transient phase of VCC switching on, or switching off, the value of VCC is monitored and the outputs of the circuit are inhibited if it is too low. In order to have a very good powersupplyrejection, the circuit is internally powered by several internal voltage references (The unique typical value of which is 8V). Two of these voltage references are externally accessible, one for the vertical part and one for the horizontal part. These voltage references can be used for the DC control voltages applied on the concerned pins by the way of potentiometers or digital to analog converters (DAC's). Furthermore it is possible to filter the a.m. voltage references by the use of external capacitor connected to ground, in order to minimize the noise and consequently the "jitter" on vertical and horizontal output signals. DC Control Adjustments The circuit has 10 adjustment capabilities : 3 for the horizontal part, 1 for the SMPS part, 2 for the E/W correction, 4 for the vertical part. The corresponding inputs of the circuit has to be driven with a DC voltage typically comprised between 2 and 6V for a value of the internal voltage reference of 8V. More precisely, the control voltages have to be maintained between VREF/4 and 3/4 VREF. The application of control voltages outside this range is not dangerousfor the circuit but the good operation is not guaranted (except for Pin 2 : duty cycle adjusment. See outputs inhibition paragraph). Figure 5 : Example of Practical DC Control Voltage Generation
VREF 10k
9103-08.AI
The input currents of the DC control inputs are typically very low (about a few A). Depending on the internal structure of the inputs, the input currents can be positive or negative (sink or source). HORIZONTAL PART Input section The horizontal input is designed to be sensitive to TTL signals typically comprised between 0 and 5V. The typical threshold of this input is 1.6V. This input stage uses an NPN differential stage and the input current is very low. Concerning the duty cycle of the input signal, the following signals may be applied to the circuit. Figure 6
Z T
Z
9103-07.AI
Using internal integration, both signals are recognized on condition that Z/T 25%. Synchronisation occurs on the leading edge of the rectified signal. The minimum value of Z is 0.7s. Figure 7 : Input Structure
HSYNC
1.6V
22k
DC Control Voltage
10k
9103-06.AI
PLL1 The PLL1 is composed of a phase comparator, an external filter and a Voltage Controlled Oscillator (VCO). The phase comparatoris a "phase frequency" type, designed in CMOS technology. This kind of phase detector avoids locking on false frequencies. It is followed by a "charge pump", composed of 2 current sources sink and source (I = 1mA typ.)
11/27
TDA9103
Figure 8 : Principle Diagram
C Lockdet 13 LOCKDET
High
Eini 35
Filter R0 C0 12 11 10
Horizontal 17 Input
INPUT INTERFACE
COMP1
E2 Low
CHARGE PUMP
PLL INHIBITION Horizontal Adjust 15 PHASE ADJUST
3.2V
VCO
OSC
9103-09.AI 9103-58.EPS
The dynamic behaviour of the PLL is fixed by an external filter which integrates the current of the charge pump. A "CRC" filter is generally used. PLL1 is inhibited by applying a high level on Pin 35 (PLLinhib) which is a TTL compatible input. The inhibition results from the opening of a switch located between the charge pump and the filter (see Figure 8). The VCO uses an external RC network. It delivers a linear sawtooth obtained by charge and discharge of the capacitor, by a current proportionnal to the current in the resistor. typical thresholds of sawtooth are 1.6V and 6.4V. Figure 9
PLL1F 12
The control voltage of the VCO is typically comprised between 1.6V and 6V. The theoretical frequency range of this VCO is in the ratio 1 3.75, but due to spread and thermal drift of external components and the circuit itself, the effective frequency range has to be smaller (e.g. 30kHz 82kHz). Inthe absenceof synchronisationsignal the control voltage is equal to 1.6V typ. and the VCO oscillates on its lowest frequency (free frequency). The synchro frequencyhas to be always higher than the free frequency and a margin has to be taken. As an example for a synchro range from 30kHz to 82kHz, the suggested free frequency is 27kHz. To compensate for the spread of external components and of the circuit itself, the free frequency may be adjusted by a DC voltage on Pin 14 (Fmin adjust) (see Figure10 for details). The PLL1 ensures the coincidence between the leading edge of the synchro signal and a phase reference obtained by comparison between the sawtooth of the VCO and an internal DC voltage adjustable between 2.4V and 4V (by Pin 15). So a 45 phase adjustment is possible.
Figure 10 : Details of VCO and Fhmin Adjustment
FHMINADJ
14
9103-10.AI
I0 2 6.4V RS FLIP FLOP
a Loop 12 Filter
I0
(0.8V < a < 1.2V)
11
4 I0 2
1.6V
(1.6V < V12 < 6V) R0 C0
10
6.4V 1.6V 0 0.75T T
12/27
TDA9103
Figure 11 : Safety Functions Block Diagram
V CC Checking V CC 30 REF 30 + SMPS Output Inhibition
XRAY Protection XRAY 30 V CCoff 30 S Q R H Output Inhibition
PLL-Unloocked 30
Inhibition H-duty Cycle 30 1V 30 +
V Output Inhibition
Flyback 30 0.7V 30
+
Blanking
9103-21.AI
Figure 12 : LOCK/UNLOCK Block Diagram
20k H-Lock CAP 13 6.5V 220nF
The TDA9103 also includes a LOCK/UNLOCK identification block which sense in real-time wheather the PLL is locked on the incomming horizontal sync signal or not. The resulting information is available on safety blanking output (Pin 23) where it is mixed with others information (see Figure 11). The block diagram of the LOCK/UNLOCK function is described in Figure 12. The NOR1 gate is receiving the phase comparator output pulses (which also drives the charge pump). When the PLL is locked, on point A there is a very small negative pulse (100ns) at each horizontal cycle, so after R-C filter, there is a high level on Pin 13 which force SBLK to high level (provided other inputs on NOR2 are also at low level). When the PLL is unlocked, the 100ns negative pulse on A becomesmuch larger and consequently the average level on Pin 13 will decrease. When it reaches 6.5V, point B goes to high level forcing NOR2 open collector output to "0". The status of Pin 13 is approximately the following : - Near 0V when there is no H-SYNC, - Between 0 and 4V with H-SYNC frequency differ-
ent from VCO, - Between 4 and 8V when H-SYNC frequency = VCO frequency but not in phase, - Near to 8V when PLL is locked. It is important to notice that Pin 13 is not an output pin and must only be used for filtering purpose (see Figure 12). Figure 13 : PLL1 Timing Diagram
H Osc Sawtooth 0.75T 0.25T 6.4V 2.4V9103-16.AI
Phase REF1 is obtained by comparison between the sawtooth and a DC voltage adjustable between 2.4V and 4V. The PLL1 ensures the exact coincidence between the signals phase REF and HSYNS. A 45 phase adjustment is possible.
13/27
9103-59.EPS
From Phase Comparator
NOR1
A
B
NOR2
23 SBLK OUT
TDA9103
PLL2 Figure 14 : Dual PLL Block Diagram
C Lockdet 13 LOCKDET
High
Eini 35
Filter R0 C0 12 11 10 HFREQ
Horizontal 17 Input
INPUT INTERFACE
COMP1
E2 Low
CHARGE PUMP
PLL INHIBITION Horizontal Adjust 15 PHASE ADJUST
VCO
FAJUST
14
Freq Adjust
OSC 3.2V
Cap Adjust Rapcyc PH12 2 1
High
E2
RAP CYC
VA VB
CHARGE PUMP
Low
COMP2
E1
GENPULSE FLYBACK 3 Flyback
BUFFER
20 SortEM
The PLL2 ensures the coincidence between the leading edge of the shaped flyback signal and a phase reference signal obtained by comparison of the sawtooth of the VCO and a constant DC voltage (3.2V) (see Figure 15). Figure 15 : PLL2 Timing Diagram
H Osc Sawtooth 0.75T 0.25T 6.4V 3.2V
0.5mA (typ.) output current. The flyback input is composed of an NPN transistor. This input has to be current driven. The maximum recommanded input current is 2mA (see Figure 16). Figure 16 : Flyback Input Electrical Diagram
400 HFLY 3 20k
9103-11.AI
Q1
1.6V
GND 0V
Flyback Shapped Flyback Phase REF2 H Drive Ts Duty Cycle
9103-57.AI
Phase REF2 is obtained by comparison between the sawtooth and a 3.2V (constant). The PLL2 ensures the exact coincidence between the signals phase REF2 and the flyback signal. The duty cycle of H-drive is adjustable between 30% and 50%.
The phase comparator of PLL2 is similar to the one of PLL1, it is followed by a charge pump with a
14/27
Output Section The H-drive signal is transmitted to the output through a shaping block ensuring a duty cycle adjustable from 30% to 50%. In order to ensure a reliable operation of the scanning power part, the output is inhibited in the following circumstances : - VCC too low. - Xray protection activated. - During the flyback. - Output voluntarily inhibited. The output stage is composed of a Darlington NPN bipolar transistor. Both the collector and the emitter are accessible.
9103-15.AI
PWM
LOGI PWM
21 SortCOLL
TDA9103
Figure 17 : Output stage simplified diagram, showing the two possibilities of connection
21 VCC
The reset of this protection is obtained by VCC switch off. S Correction. S Outputs In the case where the "S correction" of the horizontal scanning is performed using capacitors, it is necessary to switch capacitors when the frequency changes.
20
H-DRIVE
For this the outputs S1, 2, 3 and 4 (Pins 9, 8, 7 and 16) give an indication about the horizontalfrequency by monitoring thecontrolvoltage of the VCO (Pin 12). The switching of the S outputs occurs for the following value of the control voltage.
S1 S2 2V 2.4V 3V 3.7V
V CC
21 VCC H-DRIVE
S3 S4
9103-12.AI / 9103-13.AI
20
The use of comparators with hysteresis avoids erratic switching of the Sout outputs if the control voltage of the VCO remains very close to a switching reference level.
The output Darlington is in off-state when the power scanning transistor is also in off-state. The maximum output current is 20mA, and the correspondingvoltage drop of the output darlington is 1.1V typically. It is evident that the power scanning transistor cannot be directly driven by the integrated circuit. An interface has to be designed between the circuit and the power transistor which can be of bipolar or MOS type. Outputs inhibition : the application of a voltage lower than 1V (typ.) on Pin 2 (duty cycle adjust) inhibits the horizontal, vertical and SMPS outputs. This is not memorised. X-ray protection : the activation of the X-ray protection is obtained by application of a high level on the X-ray input (>1.6V). Consequences of X-ray protection are : - Inhibition of H drive output. - Inhibition of SPMS output. - Activation of safety blanking output.
SMPS This unit generates the supply voltage for the horizontal scanning system. This supply voltage is approximately proportional to the H frequency in order to keep the scanning amplitude constant when the frequency changes. More precisely the amplitude regulation is obtained by detecting and regulating the "flyback" amplitude or EHT value. The power supply is a step-up converter and it uses the "current-mode" regulation principle. The power supply works in synchronism with the horizontal scanning. The switching power transistor (external to the TDA9103) is switched on at the beginning of the positive slope of the horizontal sawtooth. It is switched off as required by the integrated regulator. The current in the switching power transistor is monitored and limited, and the ratio Ton/Ton+Toff of the power transistor is limited to 75% typically providing a very good reliability to the power supply.
15/27
TDA9103
Figure 18 : SMPS Block Diagram
ISENSE 42 H-amp Reg-in 39 40 EA + + Clamp H-FREQ
S Basc R Buffer 22 SMPS OUT
VREF
RAP CYC
41 Compensation
Figure 19 : SMPS Timing Diagram
0.75T 0.25T 6.4V H Osc Sawtooth 1.6V SMPS Drive SMPS Current Error Amplifier Output (1.2V Max)
9103-19.AI 9103-20.EPS
Figure 20 : H Scanning Amplitude Regulation Example
Step-up Converter U0 TDA9103 VREF 4.8V SWITCHING REGULATOR Usyst H S can ning P art H yoke
Hamp Adjust
HDRIVE Usyst is a pproximatively proportiona l to Hfreq
Flyba ck Pe a k Detection a nd Re gulation
The following functions are implemented in the TDA9103 : - A DC controlled variable gain amplifier allowing a variation of 14% of the voltage reference. This is used to set the horizontal image amplitude. - An erroramplifier, the non inverting input of which is connected to the above mentioned adjustable voltage reference. The inverting input and the output of the error
amplifier are externally accessible. - A comparator which determines the conduction of the external transistor by comparing the output voltage of the error amplifier and the voltage applied on Pin 42 (ISENSE), which is the image of the current in the power transistor (current mode principle). - A flip-flop which memorizes the on or off state of the power transistor. - An output buffer stage (open collector).
16/27
9103-18.AI
TDA9103
PARABOLA GENERATION FOR EAST-WEST CORRECTION (see Figure 21) Starting from the vertical ramp a parabola is generated for E/W correction. The core of the parabola generator is an analog multiplier which generates a current in the form : I = k (VRAMP - VMID)2 Where VRAMP is the vertical ramp, typically comprised between 2 and 5V, VMID is a DC voltage with a nominal value of 3.5V, but adjustable in the range 3.2V 3.8V in order to generate a dissymmetric parabola if required (keystone adjustment). The current is converted into voltage through a variable gain transresistance amplifier. The gain, controlled by the voltage on Pin 37 (E/W-AMP) can be adjusted in the ratio 3/1. The parabola is available on Pin 36 by the way of an emitter follower which has to be biased by an external resistor (10k). It must be AC coupled with external circuitry. The typical parabola amplitude (AC), with the DC Figure 21 : Parabola Generation Principle
Analog. Multiplier I Vertical Ramp 38 E/W-CENT 36
9103-14.AI
control voltages V37 and V38 set to 4V, is 2V. It is important to note that the parasitic parabola during the discharge of the vertical oscillator capacitor is suppressed. VERTICAL PART (see Figure 22) The vertical part generates a fixed amplitude ramp which can be affected by a S correction shape. Then, the amplitude of this ramp is adjusted to drive an external power stage. The internal reference voltage used for the vertical part is available between Pin 26 and Pin 24. It can be used as voltage reference for any DC adjusment to keep a high accuracy to each adjustment. Its typical value is : V26 = VREF = 8V. The charge of the external capacitor on Pin 27 (VCAP) generates a fixed amplitude ramp between the internal voltages, VL (VL = VREF/4) and VH (VH = 5/8 VREF).
+
or 37 E/W-AMP
Figure 22 : Vertical Part Block Diagram
Charge Current R VREF Disch. V-SYNC 34 SYNCHRO OSCIL Osc Cap 27 25 Sampling Cap 19R Transconductance Amplifier VREF
29 S-CENTER 28 S-AMP S Correction 30 VERT-OUT 31 VERT-AMP
9103-17.AI
Parabola Generator 38 KEYST 37 EW-AMP
36 EW-OUT
17/27
TDA9103
Function When the synchronisation pulse is not present, an internal current source sets the free running frequency. For an external capacitor, COSC = 180nF, the typical free running frequency is 84Hz. Typical free running frequency can be calculated by : f0 (Hz) = 1.5 10-5 1 COSC (nF) Endly, the amplitude of this S corrected ramp can be adjusted by the voltage applied on Pin 31 (VAMP). The adjusted ramp is available on Pin 30 (VOUT) to drive an external power stage. The gain of this stage is typically 30% when voltage applied on Pin 31 is in the range VREF/4 to 3/4 VREF. The DC value of this ramp is kept constant in the frequency range , for any correction applied on it. Its typical value is : VDCOUT = VMID = 7/16 VREF. A DC voltage is available on Pin 32 (VDCOUT). It is driven by the voltage applied on Pin 33 (VPOS). For a voltage control range between VREF/4 and 3/4 VREF, the voltage available on Pin 32 is : VDCOUT = 7/16 VREF 300mV. So, the VDCOUT voltage is correlated with DC value of VOUT. It increases the accuracy when temperature varies. Basic Equations In first approximation, the amplitude of the ramp on Pin 30 (VOUT) is :
VOUT - VMID = (VCAP - VMID) [1 + 0.16 (VAMP - VREF/2)]
A negative or positive TTL level pulse applied on Pin 34 (VSYNC) can synchronise the ramp in the frequency range [fmin, fmax]. This frequency range dependson the external capacitor connectedon Pin 27. A capacitor in the range [150nF, 220nF] is recommanded for application in the following range : 50Hz to 120Hz. Typical maximum and minimum frequency, at 25C and without any correction (S correction or C correction), can be calculated by : fmax = 2.5 f0 fmin = 0.33 f0 If S or C corrections are applied, these values are slighty affected. If an external synchronisation pulse is applied, the internal oscillator is automaticaly caught but the amplitude is no more constant. An internal correction is activated to adjust it in less than half a second: the highest voltage of the ramp on Pin 27 is sampled on the sampling capacitor connected on Pin 25 (VAGCCAP) at each clock pulse and a transconductance amplifier generates the charge current of the capacitor. The ramp amplitude becomes again constant. It is recommanded to use a AGC capacitor with low leakage current. A value lower than 100nA is mandatory. DC Control Adjustments Then, a S correction shape can be added to this ramp. This frequency independent S correction is generated internally; its amplitude is DC adjustable on Pin 28 (VSAMP) and it can be centered to generate C correction, according to the voltage applied on Pin 29 (VSCENT). It is non effective for VSAMP lower than VREF /4 and maximum for VSAMP = 3/4 VREF.
with VMID = 7/16 VREF ; typically 3.5V VMID is the middle value of the ramp on Pin 27 VCAP = V27 , ramp with fixed amplitude. On Pin 32 (VDCOUT), the voltage (in volts) is calculated by : VDCOUT =VMID + 0.16 (VPOS - VREF/2). VPOS is the voltage applied on Pin 33. The center of the S correction can be approximatively calculated according to the voltage applied on Pin 29 (VSCENT) : VCENTER = VMID + 0.25 (VSCENT - VREF/2) This is an internal voltage used to adjust the C correction. The S correction can be adjusted along the ramp according to this parameter. It is ineffective when VSAMP is lower than VREF/4. The current available on Pin 27 (when VSAMP = VREF /4) is : IOSC = 3/8 VREF COSC f COSC : capacitor connected on Pin 27 f synchronisation frequency The recommanded capacitor value on Pin 25 (VAGC) is 470nF. Its assumes a good stability of the internal closed loop.
18/27
TDA9103
INTERNAL SCHEMATICS Figure 23
VREF Q1 Q4 VCC D22 1 PLL2C Q5 Q6 Q6
9103-22.AI
Figure 24
VCC D25 HDUTY 2 D24 Q9 Q8
D23
M7
9103-23.AI
Figure 25
Figure 26
VCC
VCC D26 HFLY 3 D27 Q13
Q15 Q16
VCC D29 5 HREF
9103-24.AI 9103-25.AI
D28
Figure 27
VCC D31 D30 M20
9103-26.AI
Figure 28
Q33
VCC D34 10 C0 D35
S4/S3/S2/S1 Pins 6-7-8-9
19/27
9103-27.AI
Q32
TDA9103
INTERNAL SCHEMATICS (continued) Figure 29 Figure 30
M5 Q46 R0 11 Q69
9103-28.AI
M4
M6
VCC D10 PLL1F 12 D9 Q7 Q8
Figure 31
VCC D13
Figure 32
VCC D20 Q15 14 FH-MIN D19
9103-30.AI 9103-31.AI
13 HLOCK-CAP M11 D14
Q17
Figure 33
Figure 34
VCC
VCC D24
Q22 Q21 Q23
D27 Q26 16 XRAY-IN D28
9103-32.AI 9103-33.AI
15 H-POS D25
Figure 35
Figure 36
VCC D7
VCC D2 Q1 D0 17 HSYNC
D6 Q3 Q4 D8
21 H-OUTCOLL
VCC
20 H-OUTEM
9103-34.AI 9103-35.AI
D9
20/27
9103-29.AI
TDA9103
INTERNAL SCHEMATICS (continued) Figure 37 Figure 38
VCC
VCC NMOS VAGCCAP 25 PMOS
NMOS
NPN
NPN
PMOS
9103-36.AI
NPN
26 VREF
9103-37.AI
Figure 39
VREF PNP VCC 12V PNP
VCC PNP VREF NPN NPN NPN NMOS
9103-38.AI
VCAP 27
Figure 40
VREF PNP
Figure 41
VREF PNP
VCC
PNP
VS-AMP 28
PNP
VCC NPN NPN NPN
9103-40.AI
NPN
NPN
9103-39.AI
VS-CENT 29
21/27
TDA9103
INTERNAL SCHEMATICS (continued) Figure 42
VCC NPN 30 VOUT PNP
9103-41.AI
Figure 43
VREF VCC
NPN
31 V-AMP
NPN
9103-42.AI
Figure 44
VCC NPN PNP 32 VDCOUT
Figure 45
VCC VREF PNP
V-POS 33
PNP
NPN
PNP
9103-43.AI
NPN
NPN
9103-44.AI
Figure 46
Figure 47
VCC
VREF PNP
VREF NPN
VCC
36 E/WOUT NPN
VSYNC 34
PNP
NPN
9103-45.AI 9103-46.AI
22/27
TDA9103
INTERNAL SCHEMATICS (continued) Figure 48
VCC VREF PNP PNP E/W-AMP 37 NPN KEYST 38 PNP
Figure 49
VCC VREF PNP
NPN
9103-47.AI
NPN
NPN
9103-48.AI
Figure 50
Figure 51
VCC
VCC D28 Q24 Q26 D27 39 B+-ADJ
9103-49.AI
Q23
D21 REGIN 40 D22
9103-50.AI
Q20
Q19
Figure 52
VCC D18 41 COMP Q14 Q15
9103-51.AI
Figure 53
Q16
VCC D13 I SENSE 42 D12
9103-52.AI
Q10
D17
23/27
R10 3.9 k
R13 3.9 k
R16 3.9 k
R19 3.9 k
R25 3.9 k
R1 3.9 k
R4 3.9 k
R7 3.9 k
R28 3.9 k
R3 10 k
R6 1 0 k
R9 1 0 k
R1 2 10k
R1 8 10k
R20 120 k
R2 1 10k R23 120 k R22 3.9 k
R74 10k
R73 10k
R2 1 2 0k
R5 1 2 0k
R8 1 2 0k
R11 12 0k
R1 5 10k R17 120 k
R1 4 12 0k
R2 4 10k R26 120 k
R2 7 10k R29 120k
R3 0 10k
D4 1N4148
C48
1nF
R80 2 .7 k
24/27
C23 220F 63V
VM
J12
1
+
T2 J20 G 5446-00
R63 1k
+12V
C22 100 F
1
J11
TDA9103
+
Q7
D3 BYT 13-800
Q6 IR430F R64 3.3k R65
J1b J3b
1234567
J2b
+
R62 1k
B+
BC547
1
33k
C25 22 F 250V
1234
1234
0/5V to 2/6V INTERFACE
HSIZE
KEYST
CCOR PINCSH VSHIFT
VSIZE
R60 R66
Q5 BC557
+12V
BPLUS
HDF FHMIN 1k
1W C47 10nF C46 10nF
SCOR
33
1.5k
HSHIFT
C24 220pF 400V R61
VP R79
HFLY
HFLY
APPLICATION DIAGRAM
R72 1k
C33 100pF B+ CONVERTER
75k
R78 22k
J25
1
EHT FEEDBACK
HREF
VREF R75
+12V C39
+
1F
R76 1 42 C1 22nF
IC1
3.3k
R52 Q8 BC547 Q3
+
R53
R55
VP
R68 1M
41
R49
10k
10k
1k
10k
2
TP9
1.5k
47k
Q4 BC547 BC547 R57 1/2W R59
R58
J24
on
+
off
C35 C29 470pF 4 5 6 7 8 35 34 33 32 31 30 29 28 TP1 C4 16 27 150nF C27
+
R71
+
R67 22k
1 2 3 12k
C21 10 F
C36 3 39 38 37 36 40
J18 HFLY 1 C29 100nF C30 47 F
10k 1F +
C38 1F + C37 1 F +
S1
1F
+
C34
1F R48 R77 10k 1k
C45 220pF
2.2 1W C44 220pF
R50 R56
E/W
HREF
1k
R51 10k
R54 470
2.7k
Q9 TIP122
J17
E/W POWER STAGE
+12V D1 1N4004 R37 C13 470 F
1 2 CS SWITCH 3 4 9 C2 10 680pF 5% 11 C3 10nF
+
C32 100nF -12V TP11
J21
C43 1F +
1
5.6k
R70 12k
7 1
2 6
R32 7.5k
12 C6 220nF 13 14 15 VREF
C42 1F + R36 12k C40 1 F + C41 1 F +
+ C12 100 F 35V 3
C10 100nF
5 4
J23 V YOKE R41 C11 470pF -12V
C7 4.7 F
+ R31 1.8k
T D A 9 1 0 3
1.5
C15 220nF C14 470 F
R39
1 2 3 220 1/2W CON2
R33
10k
+ R36 5.6k
C11 470pF
R40
XRAY IN
TP2 17 C5 18 25 470nF 19 24 23 22 20 21 100nF C28 47 F 26
1
1/2W
HSYNC
TP3
VERTICAL DEFLECTION STAGE
J2
+12V
+12V R47b +12V R69
VP
J3 1
C8 100 F
+
C9 100nF
33
3W
R47a 47 3W
T1
J22
J19
TP5
TP4
3.9k
1
TP8 R35 Q10 BC547
C20 100 F
+
HDRIVE
G 5576-01
1 2 3
BLK
TP6
1k
R44 10
Q2 STD5N20
VSYNC
TP7 Q1
R46 R45
J5
560 BC557 22k
C19 1nF
HORIZONTAL DRIVER STAGE
9103-53.EPS
TDA9103
A demonstration board has been developped by SGS-THOMSON and is available through your usual SGS-THOMSON office. This board has been designed in order to give first the possibility to evaluate the TDA9103 in STAND ALONE, and then to be easily connected to an existing monitor. In stand alone evaluation, for exemple, flyback simulator is implemented in order to be able to Figure 54 close the 2nd PLL loop, potentiometers are also present to easily adjust all functions. Then for testing in a real application, the upper part of the board can be detached and the remaining part can be connected to real application. In addition to this, the application board has been volontary designed separating clearly all the blocks. This led to quite large PCB but give much more space for measuring anything on the board.
25/27
9103-60.TIF
TDA9103
Figure 55
TDA9103
26/27
9103-61.EPS
TDA9103
PACKAGE MECHANICAL DATA 42 PINS - PLASTIC PACKAGE
E E1
A1
A2
B
B1
e
L
A
e1 e2
D c E 42 22
.015 0,38 Gage Plane
1
21
SDIP42
e3 e2
Dimensions A A1 A2 B B1 c D E E1 e e1 e2 e3 L
Min. 0.51 3.05 0.36 0.76 0.23 37.85 15.24 12.70
Millimeters Typ.
Max. 5.08 4.57 0.56 1.14 0.38 38.35 16.00 14.48
Min. 0.020 0.120 0.0142 0.030 0.0090 1.490 0.60 0.50
Inches Typ.
Max. 0.200 0.180 0.0220 0.045 0.0150 1.510 0.629 0.570
3.81 0.46 1.02 0.25 38.10 13.72 1.778 15.24
0.150 0.0181 0.040 0.0098 1.5 0.540 0.070 0.60
2.54
3.30
0.10
0.130
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without noti ce. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1996 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
27/27
SDIP42.TBL
18.54 1.52 3.56
0.730 0.060 0.140
PMSDIP42.EPS

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